The acronym RISC (pronounced risk), for reduced instruction set computing, represents a CPU design strategy emphasizing the insight that simplified instructions which "do less" may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly. Many proposals for a "precise" definition have been attempted, however, the term is being slowly replaced by the more descriptive load-store architecture (see below). Well known RISC families include DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC), SuperH, and SPARC.
Being an old idea, some aspects attributed to the first RISC-labeled designs (around 1975) include the discovery that compilers of the time were often unable to take advantage of features intended to facilitate coding, and that complex addressing took many cycles to perform. It was argued that such functions would better be performed by sequences of simpler instructions if this could yield implementations simple enough to cope with really high frequencies, and small enough to leave room for many registers, factoring out slow memory accesses. Uniform, fixed length instructions with arithmetics restricted to registers were chosen to ease instruction pipelining in these simple designs, with special load-store instructions accessing memory.
Reference:
http://en.wikipedia.org/wiki/RISC
